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Freeing up near-memory capacity for cache using compression techniques in a flat hybrid memory architecture
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Freeing up near-memory capacity for cache using compression techniques in a flat hybrid memory architecture

A technical paper titled “HMComp: Extending Near-Memory Capacity Using Compression in Hybrid Storage” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies.

Abstract:

“Hybrid memories, particularly the combination of a first-level near memory with high-bandwidth memory (HBM) and a second-level far memory with DRAM, can realize a large and inexpensive high-bandwidth main memory. Modern hybrid memories typically use a flat hierarchy where blocks are swapped between near memory and far memory based on bandwidth needs. However, this can result in significant overhead for metadata storage and traffic. Although using a fixed-size near memory cache and compressing data in near memory can help, valuable near memory capacity is still wasted by the cache and metadata required to manage a compressed hybrid memory.

This paper proposes HMComp, a flat hybrid memory architecture where compression techniques free up capacity in near memory that can be used as a cache for far memory data to reduce swap traffic without sacrificing storage capacity. Furthermore, through a carefully crafted metadata layout, we show that metadata can be stored in lower-cost far memory, avoiding wasting capacity in near memory. Overall, HMComp provides up to 22% single-threaded performance speedup, 13% on average, and up to 60% swapping traffic reduction, 41% on average, compared to flat hybrid memory designs.”

The technical document can be found here. Published in June 2024.

Shao, Qi, Angelos Arelakis, and Per Stenström. “HMComp: Extending Near-Memory Capacity Using Compression in Hybrid Storage.” In Proceedings of the 38th ACM International Conference on Supercomputing, pp. 74-84. 2024, Kyoto, Japan. ACM, New York, NY, USA, 11 pages.
https://doi.org/10.1145/3650200.3656612

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